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RF9986
8
Typical Applications
* CDMA/TDMA/DCS1900 PCS Systems * PHS 1500/WLAN 2400 Systems * General Purpose Down Converter * Micro-Cell PCS Base Stations * Portable Battery-Powered Equipment
PCS LOW NOISE AMPLIFIER/MIXER
Product Description
The RF9986 is a monolithic integrated receiver front-end for PCS, PHS, and WLAN applications. The IC contains all of the required components to implement the RF functions of the receiver front-end except for the passive filtering and LO generation. It contains an LNA (low-noise amplifiers), a double-balanced Gilbert cell mixer, a balanced IF output, an LO isolation buffer amplifier, and an LO output buffer amplifier for providing the buffered LO signal as an output. The IC is designed to operate from a single 3.6V power supply.
0.157 0.150
0.0098 0.0040
1
0.344 0.337
0.012 0.008
0.025 0.0688 0.0532
0.2440 0.2284 8MAX 0MIN
8
0.0098 0.0075
0.050 0.016
Optimum Technology Matching(R) Applied
Si BJT Si Bi-CMOS
NC 1 VCC1 2 VCC2 3 GND1 4 LNA IN 5 GND2 6 GND3 7 NC 8 GND4 9 VCC3 10 LO BUFF EN 11 LO IN 12
u
Package Style: SSOP-24
GaAs HBT SiGe HBT
GaAs MESFET Si CMOS
24 NC 23 GND9 22 VCC4 21 GND8 20 LNA OUT 19 GND7 18 MIX RF IN 17 GND6 16 IF15 IF+ 14 GND5 13 LO BUFF OUT
Features
* Complete Receiver Front-End * Extremely High Dynamic Range * Single 3.6V Power Supply * External LNA IP3 Adjustment * 1500MHz to 2500MHz Operation
Ordering Information
RF9986 RF9986 PCBA PCS Low Noise Amplifier/Mixer Fully Assembled Evaluation Board
Functional Block Diagram
RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA
Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com
Rev B1 010717
8-131
FRONT-ENDS
RF9986
Absolute Maximum Ratings Parameter
Supply Voltage Input LO and RF Levels Ambient Operating Temperature Storage Temperature
Rating
-0.5 to 7.0 +6 -40 to +85 -40 to +150
Unit
VDC dBm C C
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
Parameter
Overall
RF Frequency Range LO Frequency Range IF Frequency Range
Specification Min. Typ. Max.
1500 1200 DC to 500 22 -15.0 25 -10.0 2.5 2500 2500
Unit
Condition
T = 25C, VCC =3.6V, RF=1959MHz, LO=1749MHz @ -2dBm
MHz MHz MHz 1k balanced load, 2.5dB Image Filter Loss. dB dBm dB
Cascaded Performance
Cascade Conversion Gain Cascade Input IP3 Cascade Noise Figure
First Section (LNA)
Single Sideband The LNA section may be left unused. Power is not connected to pin 1. The performance is then as specified for the Second Section (Mixer). Input is internally matched for optimum noise figure from a 50 source. IP3 may be increased 10dB by connecting pin 22 to VCC through the matching inductor. The LNA's current then increases by 10mA. Other in-between IP3 vs. ICC trade-offs may be made. See pin description for pin 20.
8
FRONT-ENDS
Noise Figure Input VSWR Input IP3
1.4 <2:1 +5.5
dB
dBm
Gain Reverse Isolation Output VSWR
12 23 <1.5:1 5.5 1.5:1 -0.5 15.5 1 -5 to +3 -4 -25 30 20 <2:1 2.7 3.65% 5 52 48
dB dB With 1k balanced load. Single Sideband
Second Section (Mixer)
Noise Figure Input VSWR Input IP3 Conversion Gain Output Impedance dB dBm dB k dBm dBm dBm dB dB
Balanced
LO Input
LO Input Range LO Output Level LO to RF (Mix In) Rejection LO to IF1, IF2 Rejection LO Input VSWR +1 -20 Buffer On, -2dBm input Buffer Off, -2dBm input
Single ended 5.0 V mA mA mA
Power Supply
Voltage Current Consumption LNA only LNA + Mixer, LO Buffer On LNA + Mixer, LO Buffer Off
8-132
Rev B1 010717
RF9986
Pin 1 2 Function NC VCC1 Description
No connection. This pin may be grounded (recommended) or left open. Supply voltage for the mixer and RF buffer amplifier. External RF bypassing is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. Supply voltage for the LNA. External RF bypassing is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. Ground connection for the LNA. For best performance, keep traces physically short and connect immediately to ground plane. RF Input pin for the LNA. This pin is internally DC-blocked and internally matched for minimum noise figure (NOT for minimum VSWR), given a 50 source impedance. Same as pin 4. Ground connection for the RF buffer amplifier. For best performance, keep traces physically short and connect immediately to ground plane. No connection. This pin may be grounded (recommended) or left open. Same as pin 7. Supply voltage for both LO buffer amplifiers. External RF bypassing is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. Enable pin for the LO output buffer amplifier. This is a digitally controlled input. A logic "high" (3.1V) turns the buffer amplifier on, and the current consumption increases by 3mA (with -2dBm LO input). A logic "low" (0.5V) turns the buffer amplifier off. Mixer LO input pin. This pin is internally DC-blocked and matched to 50. Optional buffered LO output. This pin is internally DC-blocked and matched to 50. The buffer amplifier is switched on or off by the voltage level at pin 11. Ground connection for both LO buffer amplifiers. For best performance, keep traces physically short and connect immediately to ground plane. Open-collector IF output pin. This is a balanced output. The output impedance is set by an internal 1000 resistor to pin 16. Thus the differential IF output impedance is 1000. The resistor sets the operating impedance, but an external choke or matching inductor to VCC must be supplied in order to bias this output. This inductor is typically incorporated in the matching network between the output and IF filter. Because this pin is biased to VCC, a DC blocking capacitor must be used if the IF filter input has a DC path to ground. Same as pin 15, except complementary output. Ground connection for the mixer. For best performance, keep traces physically short and connect immediately to ground plane. Mixer RF Input Pin. This pin is internally DC-blocked and matched to 50. Same as pin 17.
150 VCC1 BIAS VCC4
Interface Schematic
3
VCC2
4 5 6 7 8 9 10
GND1 LNA IN GND2 GND3 NC GND4 VCC3
11
LO BUFF EN LO IN LO BUFF OUT GND5 IF+
LO BUFF EN
7.5 k
8
FRONT-ENDS
12 13 14 15
IF1 k
IF+
16 17 18 19
IFGND6 MIX RF IN GND7
See pin 15.
Rev B1 010717
8-133
RF9986
Pin 20 Function LNA OUT Description
LNA output pin. This is an open-collector output. This pin is typically connected to pin 22 through a bias/matching inductor. This inductor, in conjunction with a series blocking/matching capacitor, forms a matching network to the 50 image filter and provides bias (see Application Schematic). The LNA's IP3 may be increased 10dB by connecting pin 20 to VCC through the inductor. The LNA's current then increases by 10mA. Other in-between IP3 vs. ICC trade-offs may be made by connecting resistance values between VCC and the matching inductor. The two reference points for consideration are with 150 used, which is what connection to pin 22 achieves, the Input IP3 is +5.5dBm and the LNA ICC is 5mA. Using no resistance, the Input IP3 is +15.5 dBm and the LNA ICC is 15 mA. Desired operating points in between these values may be interpolated, roughly. Same as pin 17. Output supply voltage for the LNA output (pin 20). This pin is typically connected to pin 20 through a bias/matching inductor (see application schematic). External RF bypassing is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. Same as pin 17. No connection. This pin may be grounded (recommended) or left open. See pin 2.
Interface Schematic
LNA OUT
21 22
GND8 VCC4
23 24
GND9 NC
8
FRONT-ENDS
1 VCC 2 3 22 pF 4 RF IN 5 6 7 8 9 VCC LO BUFF EN (On: 3.1 V; Off: 0.5 V) LO IN 22 pF 10 11 12
Application Schematic
24 23 22 pF 22 21 20 1.8 pF 19 18 17 22 pF 16 C2 15 22 pF 14 13 1 nF C1 L1 VCC ZOUT = 1 k LO BUFF OUT L1 and C2 serve dual purposes. L1 serves as an output bias choke, and C2 serves as a series DC block. In addition, the values of L1 and C2 may be chosen to form an impedance matching network if the IF filter's input impedance is not 1000 . Otherwise, the values of L1 and C1 are chosen to form a parallel-resonant tank circut at the IF when the IF filter's input impedance is 1000 . IF+ Measurement Reference Plane C1 RF Image Filter, 50 VCC L1 ZFILTER = 1 k 2.7 nH
1 nF
C2
Filter IF-
8-134
Rev B1 010717
RF9986
Evaluation Board Schematic (IF=210MHz)
(Download Bill of Materials from www.rfmd.com.)
1 2 P1-1 C17 1 nF J1 LNA IN C16 22 pF 3 4 5 6 7 8 C19 1 nF P1-1 P1-3 R2 1 k C23 1 nF C20 22 pF C18 22 pF 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
C10 22 pF
R3
See Note 2
P1-1 L1 2.7 nH C4 1 pF 50 strip C1 22 pF FL1 C2 22 pF 50 strip
J6 LNA OUT
50 strip
C5 22 pF 50 strip T1 5.5:1 C3 22 pF
50 strip C8 5 pF L4 47 nH
J5 MIXER IN J4 IF OUT
C29 100 pF L5 220 nH C30 100 pF
C11 1.5 pF
50 strip
J3 LO OUT
8
FRONT-ENDS
J2 LO IN
Drawing 9986400, Rev -
L3 470 nH C22 1 nF
L2 470 nH P1-1 C21 22 pF C24 4.7 F
50 strip
P1 P1-1 1 2 P1-3 3 VCC GND BUFFER ENABLE
Notes: 1. C11 is selected to fine tune L4 for IF output match at 210 MHz. 2. R3 is not normally populated. For applications requiring additional LNA IP3, see the datasheet for recommended resistance values. 3. C2 and C3 are not normally populated. If C2 and C3 are populated, the LNA and mixer can be tested independently; in this case, C1 and C5 should be removed.
Rev B1 010717
8-135
RF9986
Evaluation Board Layout 3" x 3" Assembly
8
FRONT-ENDS
Top layer
8-136
Rev B1 010717
RF9986
Bottom Layer
8
Internal Ground
FRONT-ENDS
Rev B1 010717
8-137
RF9986
8
FRONT-ENDS
8-138
Rev B1 010717

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